Supercat 2600

NOTE: Not quite up to date with latest changes in Stella

In fetcher mode, the cartridge will dynamically generate 6502 code to implement a specialized instruction set. Every instruction will be 16 bits, and will take 2 to 4 cycles to execute. Instructions will be assigned 4-5 character mnemonics to distinguish them from 6507 opcodes. Opcodes ending with "+" may have an "L" or "J" suffix to specify that they should do "Loop-test" or "Jump-loop" (see below) in addition to their normal function.

The JX10 Fetcher itself keeps three pieces of state information, all of them addresses: the next JX10 instruction, the fetcher group 0 table, the and fetcher group 1 table. All other state is manged by performing read-modify-write operations on the data in the fetcher tables, or memory pointed at by such data; any of these latter changes will be directly visible to the target application.

REST+ 3 cycles JMP $1010 This instruction takes 3 cycles to execute. A REST instruction must be done at least once every 4,000 cycles or the Atari may malfunction. It translates into JMP $1010. QUIT addr (EXITS) JMP addr Generates an "JMP a" instruction and returns to normal code execution. LIMA value LIMX value LIMY value 2 cycles LDA #value LDX #value LDY #value Load A, X, or Y with an 8-bit immediate value LDFA group,fetcher,inc LDFX group,fetcher,inc LDFY group,fetcher,inc 2 cycles LDA #data LDX #data LDY #data Load A, X, or Y from fetcher #f of group #g and increment it by i. (lda #imm, etc.) SDRA+ addr SDRX+ addr SDRY+ addr SDRQ+ addr 3 cycles STA addr STX addr STY addr SAX addr Store A, X, Y, or (A&X) to specified TIA address SSDA+ addr SSDX+ addr SSDY+ addr SSDQ+ addr 4 cycles STA.w addr STX.w addr STY.w addr SAX.w addr As above, but takes 4 cycles. SDFR group,fetcher,inc 3 cycles STA addr STX addr STY addr SAX addr Get a byte from fetcher #f or group #g, increment it by i, generate a STA, STX, STY, or SAX instruction. Use top two bits of fetched value to select instruction; remaining 6 bits for address. SSFR group,fetcher,inc 4 cycles STA.w addr STX.w addr STY.w addr SAX.w addr As above, but takes 4 cycles (sta abs, etc.) TSTS addr,g,f 3 cycles BIT addr Read specified address and store the result to RAM pointed at by the specified fetcher (single-increment mode only). Useful for collision detection. TSTI addr,group,fetcher 3 cycles BIT addr Read the specified address and increment the upper byte of the indicated fetcher if bit 7 is set, and/or the lower byte if bit 6 is set. Useful for paddles.

The system has two fetcher-pointers. To perform a fetch-retrieval (e.g. for "LDFA") the system selects one of the pointers using the "g" bit. It then performs the following logic:

addr1 = ptr + f*2 addr2 = memw[addr1] dat = mem[addr2] generate opcode from dat if i<>max then addr2 += i else addr3 = memw[addr1+2] dat = mem[addr3], and update flags if dat was zero addr3++ else dat-- mem[addr3]=dat endif if addr3 is odd then addr2++ endif memw[addr1] = addr2

Loop-test and Jump-loop behavior:

dat = mem[fetchptr0-4] if dat=0 fetchptr0 = memw[fetchptr0 - 2] fetchptr1 = memw[fetchptr0-8] ' Use new value of fp0 virtpc = memw[fetchotr0-6] else dat-- memw[fetchptr0-4] = dat dat = mem[fetchptr1-4] if dat=0 fetchptr1 = memw[fetchptr1 - 2] else dat-- memw[fetchptr1-4] = dat endif if (is jump-loop instruction) virtpc = memw[fetchptr1-6] endif endif